Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The idea is to run first a single block transfer followed automatically by a linked list of DMA. The
following sequence may be used:

• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching 

for this endpoint in the UECFGn register to handle multiple OUT packet.

• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items 

: channel next descriptor address, channel destination address and channel control. The last 
descriptor should be programmed according to row 2 as shown in 

.

• Write the starting destination address in the UDDMAnADDR register.

• Program the UDDMAnNEXTDESC register.

• Program the channel byte length in the UDDMAnCONTROL register.

• Optionnaly set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.

• Program the UDDMAnCONTROL according to Row 4 as shown in 

.

The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.

As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.

Once the first DMA channel is completed (i.e : the channel byte length is reached), after one or
multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
q u e n c e ,   t h e   U D D M A n S T A T U S . C H E N   b i t   i s   a l s o   c l e a r e d ,   a n d   t h e
UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAn-
CONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if
there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when
the dma channel byte lenght is not an integral multiple of the endpoint size. Note that the
UDDMAnCONTROL.LDNXTCH bit remains to one indicating that a linked descriptor will be
loaded.

Once the new descriptor is loaded from the UDDMAnNEXTDESC memory address, the UDDM-
AnSTATUS.DESCLDSTA bit is set, and the UDDMAnCONTROL register is updated from the
memory. As a consequence, the UDDMAnSTATUS.CHEN bit is set, and the UDDMAnSTA-
TUS.CHACTIVE is set as soon as the endpoint is ready to be sourced by the DMA (received
OUT data packet).

This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in 

.

At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.

The idea is to directly run first a linked list of DMA. The following sequence may be used: The
following sequence may be used:

• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching 

for this endpoint in the UECFGn register to handle multiple OUT packet.