Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

Product codes
AT32UC3A3-XPLD
Page of 1021
737
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.16
Pipe n Control Register
Register Name:
UPCONn, n in [0..7]
Access Type:
Read-Only
Offset:
0x05C0 + (n * 0x04)
Reset Value:
0x00000000
• RSTDT: Reset Data Toggle
This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value for the current Pipe.
This bit is cleared when proceed.
• PFREEZE: Pipe Freeze
This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has 
been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been 
processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe 
requests generation.
This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation.
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
See the UECONn.EPDISHDMA bit description.
• FIFOCON: FIFO Control
For OUT and SETUP Pipe:
This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.
This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.
For IN Pipe:
This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.
This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.
• NBUSYBKE: Number of Busy Banks Interrupt Enable
This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).
• SHORTPACKETIE: Short Packet Interrupt Enable
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT (SHORTPACKETIE).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT 
(SHORTPACKETE).
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
RSTDT
PFREEZE
PDISHDMA
15
14
13
12
11
10
9
8
-
FIFOCON
-
NBUSYBKE
-
-
-
-
7
6
5
4
3
2
1
0
SHORT
PACKETIE
RXSTALLDE/
CRCERRE
OVERFIE
NAKEDE
PERRE
TXSTPE/
UNDERFIE
TXOUTE
RXINE