Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Regis-
ter (LCDR.LDATA) will be read as zero too. 

Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the
transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit
data transfers. In this case, the destination buffers are optimized. 

When a conversion is completed, the resulting 10-bit digital value is stored in the CDR register of
the current channel and in the LCDR register. Channels are enabled by writing a one to the
Channel n Enable bit (CHn) in the CHER register.

The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the
Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral
DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY
can trigger an interrupt.

Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the
DRDY bit and the EOC bit corresponding to the last converted channel.

Figure 29-2. EOCn and DRDY Flag Behavior 

Read LCDR

Write CR

With START=1

Read CDRn

Write CR

With START=1

CHn(CHSR)

EOCn(SR)

DRDY(SR)

Conversion Time

Conversion Time