Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
836
32072H–AVR32–10/2012
AT32UC3A3
31.6.4.1
WRITE_SINGLE_BLOCK operation using DMA Controller
1.
Wait until the current command execution has successfully terminated.
c.
Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set
2.
Write the block length in the card. This value defines the value block_lenght.
3.
Write the MR.BLKLEN with block_lenght value.
4.
Configure the DMA Channel in the DMA Controller.
5.
Write the DMA register with the following fields:
– Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET)
.
– Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE).
– Write a one to he DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
6.
Write a one to the DMA Transfer done bit in IER register (IER.DMADONE).
7.
Issue a WRITE_SINGLE_BLOCK command.
8.
Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set.
31.6.4.2
READ_SINGLE_BLOCK operation using DMA Controller
1.
Wait until the current command execution has successfully terminated.
d.
Check that the SR.XFRDONE bit is set.
2.
Write the block length in the card. This value defines the value block_lenght.
3.
Write the MR.BLKLEN with block_lenght value.
4.
Configure the DMA Channel in the DMA Controller.
5.
Write the DMA register with the following fields:
– Write zero to the DMA.OFFSET field
.
– Write the DMA.CHKSIZE field.
– Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI.
6.
Write a one to the IER.DMADONE bit.
7.
Issue a READ_SINGLE_BLOCK command.
8.
Wait for SR.DMADONE bit is set.
31.6.4.3
WRITE_MULTIPLE_BLOCK
1.
Wait until the current command execution has successfully terminated.
a.
Check that the SR.XFRDONE bit is set.
2.
Write the block length in the card. This value defines the value block_lenght.
3.
Write the MR.BLKLEN with block_lenght value.
4.
Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
block of data.
block of data.
5.
Program the DMA register with the following fields:
– Write the dma_offset in the DMA.OFFSET field
.
– Write the DMA.CHKSIZE field.
– Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
6.
Write a one to the IER.DMADONE bit.
7.
Issue a WRITE_MULTIPLE_BLOCK command.
8.
Wait for DMA chained buffer transfer complete interrupt.