Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Name: SR

Access Type: Read-only

Offset: 0x040

0x0C000025

This bit is set when a corrupted Boot Acknowlegde signal has been received.

This bit is cleared by reading the SR register.

This bit is set when a Boot acknowledge signal has been received.

This bit is cleared by reading the SR register.

This bit is set when at least one eight-bit data has been sent without valid information (not written).

This bit is cleared when sending a new data transfer command if the Flow Error bit reset control mode in Configuration Register 

(CFG.FERRCTRL) is zero or when reading the SR register if CFG.FERRCTRL is one.

This bit is set when at least one 8-bit received data has been lost (not read).

This bit is cleared when sending a new data transfer command if CFG.FERRCTRL is zero, or when reading the SR register if 

CFG.FERRCTRL is one.

This bit is set when the CR register is ready to operate and the data bus is in the idle state.

This bit is cleared when a transfer is in progress.

This bit is set when the FIFO is empty.

This bit is cleared when the FIFO contains at least one byte.

This bit is set when the DMA buffer transfer is completed.

This bit is cleared when reading the SR register.

This bit is set when a new block of data is received and the DMA controller has not started to move the current pending block.

This bit is cleared when reading the SR register.

31

30

29

28

27

26

25

24

UNRE

OVRE

ACKRCVE

ACKRCV

XFRDONE

FIFOEMPTY

DMADONE

BLKOVRE

23

22

21

20

19

18

17

16

CSTOE

DTOE

DCRCE

RTOE

RENDE

RCRCE

RDIRE

RINDE

15

14

13

12

11

10

9

8

TXBUFE

RXBUFF

CSRCV

SDIOWAIT

-

-

SDIOIRQB

SDIOIRQA

7

6

5

4

3

2

1

0

ENDTX

ENDRX

NOTBUSY

DTIP

BLKE

TXRDY

RXRDY

CMDRDY