Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
893
32072H–AVR32–10/2012
AT32UC3A3
33.4.2.3
DMA mode
The DMA Controller can be used in association with the AES to perform an encryption/decryp-
tion of a buffer without any action by the software during processing.
tion of a buffer without any action by the software during processing.
In this starting mode, the type of the data transfer (byte, halfword or word) depends on the oper-
ation mode.
ation mode.
The sequence is as follows:
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
Note:
The Initialization Vector Registers concern all modes except ECB.
• Configure a channel of the DMA Controller with source address (data buffer to
encrypt/decrypt) and destination address set to register IDATA1R (index is automatically
incremented and rolled over to write IDATAnR). Then configure a second channel with source
address set to ODATA1R (index is automatically incremented and rolled over to read
ODATAnR) and destination address to write processed data.
incremented and rolled over to write IDATAnR). Then configure a second channel with source
address set to ODATA1R (index is automatically incremented and rolled over to read
ODATAnR) and destination address to write processed data.
Note:
Transmit and receive buffers can be identical.
• Enable the DMA Controller in transmission and reception to start the processing.
• The processing completion should be monitored with the DMA Controller.
33.4.3
Last Output Data Mode
This mode is used to generate cryptographic checksums on data (MAC) by means of cipher
block chaining encryption algorithm (CBC-MAC algorithm for example).
block chaining encryption algorithm (CBC-MAC algorithm for example).
After each end of encryption/decryption, the output data is available either on the ODATAnR
registers for manual and automatic mode or at the address specified in the receive buffer pointer
for DMA mode.
registers for manual and automatic mode or at the address specified in the receive buffer pointer
for DMA mode.
The Last Output Data bit in the Mode Register (MR.LOD) allows retrieval of only the last data of
several encryption/decryption processes.
several encryption/decryption processes.
Therefore, there is no need to define a read buffer in DMA mode.
This data is only available on the Output Data Registers (ODATAnR).
Table 33-2.
Data Transfer Type for the Different Operation Modes
Operation Mode
Data Transfer Type (DMA)
ECB
word
CBC
word
OFB
word
CFB 128-bit
word
CFB 64-bit
word
CFB 32-bit
word
CFB 16-bit
halfword
CFB 8-bit
byte
CTR
word