Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The AES also features hardware countermeasures that can be useful to protect data against Dif-
ferential Power Analysis (DPA) attacks.

These countermeasures can be enabled through the Countermeasure Type field in the MR reg-
ister (MR.CTYPE). This field is write-only, and all changes to it are taken into account if, at the
same time, the Countermeasure Key field in the Mode Register (MR.CKEY) is correctly written
(see the Mode Register (MR) description in 

).

Note:

Enabling countermeasures has an impact on the AES encryption/decryption throughput.

By default, all the countermeasures are enabled. 

The best throughput is achieved with all the countermeasures disabled. On the other hand, the
best protection is achieved with all of them enabled.

The Random Number Generator Seed Loading bit in the CR register (CR.LOADSEED) allows a
new seed to be loaded in the embedded random number generator used for the different
countermeasures.

When an unspecified register access occurs, the Unspecified Register Detection Status bit in
the ISR register (ISR.URAD) is set to one. Its source is then reported in the Unspecified Register
Access Type field in the ISR register (ISR.URAT). Only the last unspecified register access is
available through the ISR.URAT field.

Several kinds of unspecified register accesses can occur when:

• Writing the IDATAnR registers during the data processing in DMA mode

• Reading the ODATAnR registers during data processing

• Writing the MR register during data processing

• Reading the ODATAnR registers during sub-keys generation

• Writing the MR register during sub-keys generation

• Reading an write-only register

The ISR.URAD bit and the ISR.URAT field can only be reset by the Software Reset bit in the CR
register (CR.SWRST).