Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
915
32072H–AVR32–10/2012
AT32UC3A3
34.5.2
Clocks
The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before
using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is
enabled in the Power Manager.
using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is
enabled in the Power Manager.
The ABDAC needs a separate clock for the D/A conversion operation. This clock,
GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre-
quency must be as follow:
GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre-
quency must be as follow:
where f
s
is the samping rate of the data stream to convert. For f
s
= 48 kHz this means that the
GCLK_ABDAC clock must have a frequency of 12.288MHz.
The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other.
34.5.3
Interrupts
The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC
interrupt requires the interrupt controller to be programmed first.
interrupt requires the interrupt controller to be programmed first.
34.6
Functional Description
34.6.1
How to Initialize the Module
In order to use the Audio Bitstream DAC the product dependencies given in
must be resolved. Particular attention should be given to the configuration of clocks
and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.
The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream
DAC Control Register (CR.EN).
DAC Control Register (CR.EN).
The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be
set whenever the ABDAC is ready to receive a new sample. A new sample value should be writ-
ten to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the
Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writ-
ing one to the corresponding bits in the Interrupt Clear Register (ICR).
set whenever the ABDAC is ready to receive a new sample. A new sample value should be writ-
ten to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the
Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writ-
ing one to the corresponding bits in the Interrupt Clear Register (ICR).
34.6.2
Data Format
The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can
be written to the least and most significant halfword of the Sample Data Register (SDR),
respectively.
be written to the least and most significant halfword of the Sample Data Register (SDR),
respectively.
An input value of 0x7FFF will result in an output voltage of approximately:
An Input value of 0x8000 will result in an output value of approximately:
f
GCLK
256
f
S
×
=
V
OUT
0
x
7
FFF
(
)
38
128
----------
VDDIO
38
128
----------
3 3
,
⋅
0
≈
98
V
,
=
⋅
≈
V
OUT
0
x
8000
(
)
90
128
----------
VDDIO
90
128
----------
3 3
,
⋅
2
≈
32
V
,
=
⋅
≈