Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
92
32072H–AVR32–10/2012
AT32UC3A3
9.
Watchdog Timer (WDT)
Rev: 2.4.0.1
9.1
Features
•
Watchdog timer counter with 32-bit prescaler
•
Clocked from the system RC oscillator (RCSYS)
9.2
Overview
The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is
clocked from the RC oscillator. The watchdog timer must be periodically reset by software within
the time-out period, otherwise, the device is reset and starts executing from the boot vector. This
allows the device to recover from a condition that has caused the system to be unstable.
clocked from the RC oscillator. The watchdog timer must be periodically reset by software within
the time-out period, otherwise, the device is reset and starts executing from the boot vector. This
allows the device to recover from a condition that has caused the system to be unstable.
9.3
Block Diagram
Figure 9-1.
WDT Block Diagram
9.4
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
below.
9.4.1
Power Management
When the WDT is enabled, the WDT remains clocked in all sleep modes, and it is not possible to
enter Static mode.
enter Static mode.
9.4.2
Clocks
The WDT can use the system RC oscillator (RCSYS) as clock source. This oscillator is always
enabled whenever these modules are active. Please refer to the Electrical Characteristics chap-
ter for the characteristic frequency of this oscillator (f
enabled whenever these modules are active. Please refer to the Electrical Characteristics chap-
ter for the characteristic frequency of this oscillator (f
RC
).
9.4.3
Debug Operation
The WDT prescaler is frozen during debug operation, unless the On-Chip Debug (OCD) system
keeps peripherals running in debug operation.
keeps peripherals running in debug operation.
RCSYS
CLR
Watchdog
Detector
CTRL
32-bit
Prescaler
Watchdog Reset
EN