Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
930
32072H–AVR32–10/2012
AT32UC3A3
Figure 35-2. JTAG-based Debugger
35.3.4.1
Debug Communication Channel
The Debug Communication Channel (DCC) consists of a pair OCD registers with associated
handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange
data between the CPU and the JTAG master, both runtime as well as in debug mode.
handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange
data between the CPU and the JTAG master, both runtime as well as in debug mode.
35.3.4.2
breakpoints
One of the most fundamental debug features is the ability to halt the CPU, to examine registers
and the state of the system. This is accomplished by breakpoints, of which many types are
available:
and the state of the system. This is accomplished by breakpoints, of which many types are
available:
• Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU
immediately.
• Program breakpoints halt the CPU when a specific address in the program is executed.
• Data breakpoints halt the CPU when a specific memory address is read or written, allowing
variables to be watched.
• Software breakpoints halt the CPU when the breakpoint instruction is executed.
When a breakpoint triggers, the CPU enters debug mode, and the D bit in the Status Register is
set. This is a privileged mode with dedicated return address and return status registers. All privi-
leged instructions are permitted. Debug mode can be entered as either OCD mode, running
instructions from JTAG, or monitor mode, running instructions from program memory.
set. This is a privileged mode with dedicated return address and return status registers. All privi-
leged instructions are permitted. Debug mode can be entered as either OCD mode, running
instructions from JTAG, or monitor mode, running instructions from program memory.
AVR32
JTAG-based
debug tool
PC
JTAG
10-pin IDC