Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
949
32072H–AVR32–10/2012
AT32UC3A3
Starting in Run-Test/Idle, OCD registers are accessed in the following way:
1.
Select the IR Scan path.
2.
In Capture-IR: The IR output value is latched into the shift register.
3.
In Shift-IR: The instruction register is shifted by the TCK input.
4.
Return to Run-Test/Idle.
5.
Select the DR Scan path.
6.
In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the
OCD register.
OCD register.
7.
Go to Update-DR and re-enter Select-DR Scan.
8.
In Shift-DR: For a read operation, scan out the contents of the addressed register. For a
write operation, scan in the new contents of the register.
write operation, scan in the new contents of the register.
9.
Return to Run-Test/Idle.
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
35.5.3.2
MEMORY_SERVICE
This instruction allows access to registers in an optional Memory Service Unit. The 7-bit register
index, a read/write control bit, and the 32-bit data is accessed through the JTAG port.
index, a read/write control bit, and the 32-bit data is accessed through the JTAG port.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SERVICE instruction is selected, and
toggles between address and data mode each time a data scan completes with the busy bit
cleared.
ter. The SAB starts in address mode after the MEMORY_SERVICE instruction is selected, and
toggles between address and data mode each time a data scan completes with the busy bit
cleared.
Starting in Run-Test/Idle, Memory Service registers are accessed in the following way:
1.
Select the IR Scan path.
2.
In Capture-IR: The IR output value is latched into the shift register.
3.
In Shift-IR: The instruction register is shifted by the TCK input.
4.
Return to Run-Test/Idle.
5.
Select the DR Scan path.
6.
In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the
Memory Service register.
Memory Service register.
Table 35-16. NEXUS_ACCESS Details
Instructions
Details
IR input value
10000 (0x10)
IR output value
peb01
DR Size
34 bits
DR input value (Address phase)
aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data read phase)
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data write phase)
dddddddd dddddddd dddddddd dddddddd xx
DR output value (Address phase)
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase)
eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase)
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb