Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
980
32072H–AVR32–10/2012
AT32UC3A3
Figure 36-8. SMC Signals for NRD and NRW Controlled Accesses.
36.11.2
SDRAM Signals
These timings are given for 10 pF load on SDCK and 40 pF on other signals.
Note:
1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB.
NRD
NCS
D0 - D15
NWE
A2-A25
A0/A1/NBS[3:0]
SMC7
SMC19
SMC20
SMC43
SMC37
SMC42
SMC8
SMC1
SMC2
SMC23
SMC24
SMC32
SMC7
SMC8
SMC6
SMC5
SMC4
SMC3
SMC9
SMC41
SMC40
SMC39
SMC38
SMC45
SMC9
SMC6
SMC5
SMC4
SMC3
SMC33
SMC30
SMC29
SMC26
SMC25
SMC31
SMC44
Table 36-35. SDRAM Clock Signal.
Symbol
Parameter
Conditions
Min.
Max.
Unit
1/(t
CPSDCK
)
SDRAM Controller Clock Frequency
1/(t
cpcpu
)
MHz
Table 36-36. SDRAM Clock Signal
Symbol
Parameter
Conditions
Min.
Max.
Unit
SDRAMC
1
SDCKE High before SDCK Rising Edge
7.4
ns
SDRAMC
2
SDCKE Low after SDCK Rising Edge
3.2
ns
SDRAMC
3
SDCKE Low before SDCK Rising Edge
7
ns
SDRAMC
4
SDCKE High after SDCK Rising Edge
2.9
ns
SDRAMC
5
SDCS Low before SDCK Rising Edge
7.5
ns
SDRAMC
6
SDCS High after SDCK Rising Edge
1.6
ns
SDRAMC
7
RAS Low before SDCK Rising Edge
7.2
ns
SDRAMC
8
RAS High after SDCK Rising Edge
2.3
ns
SDRAMC
9
SDA10 Change before SDCK Rising Edge
7.6
ns
SDRAMC
10
SDA10 Change after SDCK Rising Edge
1.9
ns
SDRAMC
11
Address Change before SDCK Rising Edge
6.2
ns
SDRAMC
12
Address Change after SDCK Rising Edge
2.2
ns