Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
995
32072H–AVR32–10/2012
AT32UC3A3
For higher polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
prevent any "extra" token.
39.1.4
ADC
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
39.1.5
USART
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
Fix/Workaround
None.
The NER register always returns zero.
Fix/Workaround
None.
The LIN ID is not transmitted in mode PDCM='0'
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffer is not used. The LINID must be written in the LINIR register,
after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register
will start the transfer whenever the PDCA transfer is ready.
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffer is not used. The LINID must be written in the LINIR register,
after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register
will start the transfer whenever the PDCA transfer is ready.
The LINID interrupt is only available for the header reception and not available for the
header transmission
Fix/Workaround
None.
header transmission
Fix/Workaround
None.
USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA transfer.
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA transfer.
SPI
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.