Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
292
AT32UC3A
25.9.13
Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x40
Reset value:
0x000000CC
• RXEN: Receive Enable
0: Receive is disabled.
1: Receive is enabled.
1: Receive is enabled.
• TXEN: Transmit Enable
0: Transmit is disabled.
1: Transmit is enabled.
1: Transmit is enabled.
• RXSYN: Receive Sync
0: An Rx Sync has not occurred since the last read of the Status Register.
1: An Rx Sync has occurred since the last read of the Status Register.
1: An Rx Sync has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
• CP1: Compare 1
0: A compare 1 has not occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
• CP0: Compare 0
0: A compare 0 has not occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
• RXBUFF: Receive Buffer Full
0: RCR or RNCR have a value other than 0.
1: Both RCR and RNCR have a value of 0.
1: Both RCR and RNCR have a value of 0.
• ENDRX: End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
RXEN
TXEN
15
14
13
12
11
10
9
8
–
–
–
–
RXSYN
TXSYN
CP1
CP0
7
6
5
4
3
2
1
0
RXBUFF
ENDRX
OVRUN
RXRDY
TXBUFE
ENDTX
TXEMPTY
TXRDY
32058K AVR32-01/12