Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
363
AT32UC3A
26.8.16
USART Manchester Configuration Register
Name:
MAN
Access Type:
Read-write
Offset:
0x50
Reset Value:
0x30011004
• DRIFT: Drift compensation
0: The USART can not recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
• RX_MPOL: Receiver Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PP: Receiver Preamble Pattern detected
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
1 - 15: The detected preamble length is RX_PL x Bit Period
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
31
30
29
28
27
26
25
24
–
DRIFT
1
RX_MPOL
–
–
RX_PP
23
22
21
20
19
18
17
16
–
–
–
–
RX_PL
15
14
13
12
11
10
9
8
–
–
–
TX_MPOL
–
–
TX_PP
7
6
5
4
3
2
1
0
–
–
–
–
TX_PL
RX_PP
Preamble Pattern default polarity assumed (RX_MPOL field not set)
0
0
ALL_ONE
0
1
ALL_ZERO
1
0
ZERO_ONE
1
1
ONE_ZERO
32058K
AVR32-01/12