Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
366
AT32UC3A
27. Static Memory Controller (SMC)
Rev. 1.0.0.0
27.1
Features
•
4 Chip Selects Available
•
64-Mbyte Address Space per Chip Select
•
8-, 16- or 32-bit Data Bus
•
Word, Halfword, Byte Transfers
•
Byte Write or Byte Select Lines
•
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
•
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
•
Programmable Data Float Time per Chip Select
•
Compliant with LCD Module
•
External Wait Request
•
Automatic Switch to Slow Clock Mode
•
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
27.2
Overview
The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 4 Chip Selects and a 26-bit address bus. The
32-bit data bus can be configured to interface with 8-, or16-, or 32-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. Read and write
signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
32058K
AVR32-01/12