Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
401
AT32UC3A
Figure 27-35.
Page Mode Read Protocol (Address MSB and LSB are defined in
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
NCS_RD_PULSE field of the PULSE register. The pulse length of subsequent accesses within
the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in
In page mode, the programming of the read timings is described in
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE
timings as page access timing (t
pa
) and the NRD_PULSE for accesses to the page (t
sa
), even if
the programmed value for t
pa
is shorter than the programmed value for t
sa
.
27.6.9.2
Byte Access Type in Page Mode
The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page
mode devices that require byte selection signals, configure the BAT field of the REGISTER to 0
(byte select access type).
CLK_SMC
A[MSB]
A[LSB]
NCS
NRD
D[15:0]
t
pa
NCS_RD_PULSE
t
sa
NRD_PULSE
NRD_PULSE
t
sa
Table 27-6.
Programming of Read Timings in Page Mode
Parameter
Value
Definition
READ_MODE
‘x’
No impact
NCS_RD_SETUP
‘x’
No impact
NCS_RD_PULSE
t
pa
Access time of first access to the page
NRD_SETUP
‘x’
No impact
NRD_PULSE
t
sa
Access time of subsequent accesses in the page
NRD_CYCLE
‘x’
No impact
32058K
AVR32-01/12