Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet

Product codes

ATEVK1105

573

AT32UC3A

30.8.2.11

USB Endpoint X Status Register (UESTAX)

Offset:

0x0130 + X . 0x04

Register Name:

UESTAX, X in [0..6]

Access Type:

Read-Only

Reset Value:

0x00000100

• TXINI: Transmitted IN Data Interrupt Flag

For control endpoints:

Set by hardware when the current bank is ready to accept a new IN packet. This triggers an EPXINT interrupt if

TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt and to send the packet.

For isochronous, bulk and interrupt IN endpoints:

Set by hardware at the same time as FIFOCON when the current bank is free. This triggers an EPXINT interrupt if

TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt, what has no effect on the end-

point FIFO.
The software then writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If

the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are

updated by hardware in accordance with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.

This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.

• RXOUTI: Received OUT Data Interrupt Flag

For control endpoints:

Set by hardware when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPXINT

interrupt if RXOUTE = 1.

–

BYCT

–

CFGOK

CTRLDIR

RWALL

CURRBK

NBUSYBK

–

DTSEQ

SHORT

PACKET

STALLEDI/

CRCERRI

OVERFI

NAKINI

NAKOUTI

RXSTPI/

UNDERFI

RXOUTI

TXINI

32058K

AVR32-01/12