Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet

Product codes

ATEVK1105

593

AT32UC3A

30.8.2.19

USB Device DMA Channel X Control Register (UDDMAX_CONTROL)

Offset:

0x0318 + (X - 1) . 0x10

Register Name:

UDDMAX_CONTROL

, X in [1..6]

Access Type:

Read/Write

Reset Value:

0x00000000

• CH_EN: Channel Enable

Set this bit to enable this channel data transfer.
Clear this bit to disable the channel data transfer.
This may be used to start or resume any requested transfer.
This bit is cleared by hardware when the HSB source channel is disabled at end of dma buffer.

• LD_NXT_CH_DESC_EN: Load Next Channel Descriptor Enable

Set this bit to allow automatic next descriptor loading at the end of the channel transfer.
Clear this bit to disable this feature.
If set, the dma channel controller loads the next descriptor when the UDDMAX_STATUS.CH_EN bit is reset due to soft-

ware of hardware event (for example at the end of the current transfer).

• BUFF_CLOSE_IN_EN: Buffer Close Input Enable

Set this bit to automatically closed the current dma transfer at the end of the usb OUT data transfer (received short packet).
Clear this bit to disable this feature.

• DMAEND_EN: End of DMA Buffer Output Enable

Set this bit to properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (or a Zero Length Packet) will be sent to the usb line to properly closed the

usb transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.

CH_BYTE_LENGTH

rwu

CH_BYTE_LENGTH

rwu

–

BURST_LOCK

_EN

DESC_LD_

IRQ_EN

EOBUFF_

IRQ_EN

EOT_IRQ_EN

DMAEND_EN

BUFF_CLOSE

_IN_EN

LD_NXT_CH_

DESC_EN

CH_EN

rwu

32058K

AVR32-01/12