Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
72
AT32UC3A
13.6.4
PLL Control
Name:
PLL0,1
Access Type:
Read/Write
•
RESERVED: Reserved bitfields
Reserved for internal use. Always write to 0.
•
PLLCOUNT: PLL Count
Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
automatically re-enabled after exiting a sleep mode.
•
PLLMUL: PLL Multiply Factor
•
PLLDIV: PLL Division Factor
These bitfields determine the ratio of the PLL output frequency (voltage controlled oscillator frequency f
VCO
) to the source
oscillator frequency:
f
VCO
= (PLLMUL+1)/(PLLDIV) • f
OSC
if PLLDIV > 0.
f
VCO
= 2*(PLLMUL+1) • f
OSC
if PLLDIV = 0.
If PLLOPT[1] field is set to 0:
f
f
PLL
= f
VCO.
If PLLOPT[1] field is set to 1:
f
f
PLL
= f
VCO
/ 2
.
Note that the MUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined.
•
PLLOPT: PLL Option
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range.
PLLOPT[1]: Enable the extra output divider.
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).
PLLOPT[0]: Select the VCO frequency range.
PLLOPT[1]: Enable the extra output divider.
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).
31
30
29
28
27
26
25
24
RESERVED
PLLCOUNT
23
22
21
20
19
18
17
16
RESERVED
PLLMUL
15
14
13
12
11
10
9
8
RESERVED
PLLDIV
7
6
5
4
3
2
1
0
-
-
-
PLLOPT
PLLOSC
PLLEN
32058K
AVR32-01/12