Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet

Product codes

ATEVK1105

796

AT32UC3A

41.2 Rev. J

41.2.1

PWM

1. PWM channel interrupt enabling triggers an interrupt

When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.

Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.

2. PWM counter restarts at 0x0001

The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period

3. PWM update period to a 0 value does not work

It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).

Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.

41.2.2

ADC

1. Sleep Mode activation needs additional A to D conversion

If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.

Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.

41.2.3

SPI

1. SPI Slave / PDCA transfer: no TX UNDERRUN flag

There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.

Fix/Workaround
For PDCA transfer: none.

2. SPI FDIV option does not work

Selecting clock signal using FDIV = 1 does not work as specified.

Fix/Workaround
Do not set FDIV = 1.

3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and

NCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
Fix/workaround

32058K

AVR32-01/12