Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
1000
42023E–SAM–07/2013
ATSAM4L8/L4/L2
38.6.13
Sequencer Trigger Event (STRIG)
The sources must be configured through the TRGSEL field of the SEQCFG register
(SEQCFG.TRGSEL). Selecting the event controller source allows any event controller source to
generate a sequencer trigger event (STRIG). By configuring the continuous mode, STRIG will
be generated continuously.
(SEQCFG.TRGSEL). Selecting the event controller source allows any event controller source to
generate a sequencer trigger event (STRIG). By configuring the continuous mode, STRIG will
be generated continuously.
The ADC can serve a maximum of one STRIG every 6+1 CLK_ADC periods. Extra STRIG will
be ignored. User will be informed thanks to the Sequencer Missed Trigger Event (SMTRG) field
of the SR register (SR.SMTRG). If the STRIG frequency provided by the event controller
exceeds the ADC capability, the event controller will generate an underrun status.
be ignored. User will be informed thanks to the Sequencer Missed Trigger Event (SMTRG) field
of the SR register (SR.SMTRG). If the STRIG frequency provided by the event controller
exceeds the ADC capability, the event controller will generate an underrun status.
38.6.14
Internal Timer
The ADCIFE embeds an internal 16-bit timer used as a trigger source which can be configured
by setting the ITMC field of the ITIMER register (ITIMER.ITMC).
by setting the ITMC field of the ITIMER register (ITIMER.ITMC).
Internal Timer Trigger Period= (ITMC+1)*T(CLK_ADC)
Once set as a STRIG source, the internal timer has to be started by writing a '1' in the TSTART
bit of the CR register (CR.TSTART). It can be stopped in the same way by writing a '1' in the
TSTOP bit of the CR register (CR.TSTOP). The current status of the internal timer can be read
bit of the CR register (CR.TSTART). It can be stopped in the same way by writing a '1' in the
TSTOP bit of the CR register (CR.TSTOP). The current status of the internal timer can be read
Unipolar mode
without gain and
without hystere-
sis
without gain and
without hystere-
sis
0 to Vref
0 to 4095 (12 bits unsigned
number)
number)
7 clock_cycles
4095*Vin/Vref
Unipolar mode
without gain and
with hysteresis
(zoom-
range[2]=1)
without gain and
with hysteresis
(zoom-
range[2]=1)
-0.05*vref to
0.95*vref
0.95*vref
0 to 4095 (12 bits unsigned
number)
number)
7 clock_cycles
4095*(Vin+0.05*vref)/Vref
Unipolar mode
without hystere-
sis and gain =2n
without hystere-
sis and gain =2n
0 to Vref/2
n
0 to 4095 (12 bits unsigned
number)
number)
7 clock_cycles for
n=1 (gain=2)
n=1 (gain=2)
10 clock_cycles
for n=6 (gain=64)
for n=6 (gain=64)
4095*(2
n
*Vin)/Vref
Unipolar mode
without hystere-
sis and with divi-
sion by 2
without hystere-
sis and with divi-
sion by 2
0 to 2*Vref
0 to 4095 (12 bits unsigned
number)
number)
7 clock_cycles
4095*(Vin/2)/Vref)
Unipolar mode
with hysteresis
and gain =2n
with hysteresis
and gain =2n
(-0.05*Vref to
0.95*Vref) /2
0.95*Vref) /2
n
0 to 4095 (12 bits unsigned
number)
number)
7 clock_cycles for
n=1 (gain=2)
n=1 (gain=2)
10 clock_cycles
for n=6 (gain=64)
for n=6 (gain=64)
4095*(2
n
*Vin+0.05*Vref)/Vre
f
Unipolar mode
with hysteresis
and with divi-
sion by 2
with hysteresis
and with divi-
sion by 2
-0.1*Vref to
1.9*Vref
1.9*Vref
0 to 4095 (12 bits unsigned
number)
number)
7 clock_cycles
4095*(0.5*Vin+0.05*Vref)/Vr
ef
ef
Operating mode
Input range
Output code range
Conversion time
Output decimal code