Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
110
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 10-2. Synchronous Clock Generation
10.6.1.1
Selecting the Main Clock Source
The common main clock can be connected to RCSYS or a set of other clock sources. For details
about the other main clock sources, refer to
about the other main clock sources, refer to
.
By default, the main clock will be connected to RCSYS. The user can connect the main clock to
an other source by writing the MCSEL field in the MCCTRL register. This must only be done
after that unit has been enabled and is ready, otherwise a deadlock will occur. Care should also
be taken that the new frequency of the synchronous clocks does not exceed the maximum fre-
quency for each clock domain.
an other source by writing the MCSEL field in the MCCTRL register. This must only be done
after that unit has been enabled and is ready, otherwise a deadlock will occur. Care should also
be taken that the new frequency of the synchronous clocks does not exceed the maximum fre-
quency for each clock domain.
10.6.1.2
Selecting Synchronous Clock Division Ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CPUDIV in CPUSEL register to one and CPUSEL in
CPUSEL register to the value, resulting in a CPU clock frequency:
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CPUDIV in CPUSEL register to one and CPUSEL in
CPUSEL register to the value, resulting in a CPU clock frequency:
f
CPU
= f
main
/ 2
(CPUSEL+1)
Similarly, the clock for the APBx can be divided by writing their respective registers. To ensure
correct operation, frequencies must be selected so that f
correct operation, frequencies must be selected so that f
CPU
≥
f
APBx
. Also, frequencies must
never exceed the specified maximum frequency for each clock domain.
CPUSEL and PBxSEL can be written without halting or disabling peripheral modules. Writing
CPUSEL and PBxSEL allows a new clock setting to be written to all synchronous clocks at the
same time. It is possible to keep one or more clocks unchanged by writing a one to the registers.
This way, it is possible to, e.g., scale CPU and speed according to the required performance,
while keeping the APBx frequency constant.
CPUSEL and PBxSEL allows a new clock setting to be written to all synchronous clocks at the
same time. It is possible to keep one or more clocks unchanged by writing a one to the registers.
This way, it is possible to, e.g., scale CPU and speed according to the required performance,
while keeping the APBx frequency constant.
For modules connected to the AHB bus, the APB clock frequency must be set to the same fre-
quency as the CPU clock.
quency as the CPU clock.
Mask
Prescaler
Main Clock
Sources
MCSEL
0
1
CPUSEL
CPUDIV
Main Clock
BPM
CPUMASK
CPU Clocks
AHB Clocks
APBx Clocks
Power Save Mode