Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
270
42023E–SAM–07/2013
ATSAM4L8/L4/L2
14.5.8
Page Buffer Operations
The flash memory has a write and erase granularity of one page; data is written and erased in
chunks of one page. When programming a page, the user must first write the new data into the
Page Buffer. The contents of the entire Page Buffer is copied into the desired page in flash
memory when the user issues the Write Page command, Refer to
chunks of one page. When programming a page, the user must first write the new data into the
Page Buffer. The contents of the entire Page Buffer is copied into the desired page in flash
memory when the user issues the Write Page command, Refer to
.
In order to program data into flash page Y, write the desired data to locations Y0 to Y31 in the
regular flash memory map. Writing to an address A in the flash memory map will not update the
flash memory, but will instead update location A%32 in the page buffer. The PAGEN field in the
Flash Command (FCMD) register will at the same time be updated with the value A/32.
regular flash memory map. Writing to an address A in the flash memory map will not update the
flash memory, but will instead update location A%32 in the page buffer. The PAGEN field in the
Flash Command (FCMD) register will at the same time be updated with the value A/32.
Figure 14-4. Mapping from Page Buffer to Flash
Internally, the flash memory stores data in 64-bit doublewords. Therefore, the native data size of
the Page Buffer is also a 64-bit doubleword. All locations shown in
the Page Buffer is also a 64-bit doubleword. All locations shown in
are therefore
doubleword locations. Since the HSB bus only has a 32-bit data width, two 32-bit HSB transfers
must be performed to write a 64-bit doubleword into the Page Buffer. The FLASHCALW has
logic to combine two 32-bit HSB transfers into a 64-bit data before writing this 64-bit data into the
Page Buffer. This logic requires the word with the low address to be written to the HSB bus
before the word with the high address. To exemplify, to write a 64-bit value to doubleword X0
residing in page X, first write a 32-bit word to the byte address pointing to address X0, thereafter
write a word to the byte address pointing to address (X0+4).
must be performed to write a 64-bit doubleword into the Page Buffer. The FLASHCALW has
logic to combine two 32-bit HSB transfers into a 64-bit data before writing this 64-bit data into the
Page Buffer. This logic requires the word with the low address to be written to the HSB bus
before the word with the high address. To exemplify, to write a 64-bit value to doubleword X0
residing in page X, first write a 32-bit word to the byte address pointing to address X0, thereafter
write a word to the byte address pointing to address (X0+4).
The page buffer is word-addressable and should only be written with aligned word transfers,
never with byte or halfword transfers. The page buffer cannot be read.
never with byte or halfword transfers. The page buffer cannot be read.
Z3
Z2
Z1
Z0
Z7
Z6
Z5
Z4
Z11
Z10
Z9
Z8
Z15
Z14
Z13
Z12
Z19
Z18
Z17
Z16
Z23
Z22
Z21
Z20
Z27
Z26
Z25
Z24
Z31
Z30
Z29
Z28
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y11
Y10
Y9
Y8
Y15
Y14
Y13
Y12
Y19
Y18
Y17
Y16
Y23
Y22
Y21
Y20
Y27
Y26
Y25
Y24
Y31
Y30
Y29
Y28
X3
X2
X1
X0
X7
X6
X5
X4
X11
X10
X9
X8
X15
X14
X13
X12
X19
X18
X17
X16
X23
X22
X21
X20
X27
X26
X25
X24
X31
X30
X29
X28
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
17
16
23
22
21
20
27
26
25
24
31
30
29
28
Page X
Page Y
Page Z
Page Buffer
64-bit data
Flash
All locations are doubleword locations