Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
277
42023E–SAM–07/2013
ATSAM4L8/L4/L2
• PAGEN[10:3] - Fuse value to write
All general-purpose fuses can be erased by the Erase All General-Purpose fuses (EAGP) com-
mand. An EAGP command is not allowed if the flash is locked by the security fuses.
mand. An EAGP command is not allowed if the flash is locked by the security fuses.
Two errors can be detected in the FSR register after issuing these commands:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
• Lock Error:
The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that
the 16 lowest general-purpose fuse bits can also be written/erased using the commands for
locking/unlocking regions, see
the 16 lowest general-purpose fuse bits can also be written/erased using the commands for
locking/unlocking regions, see
.
14.8
Security Fuses
The security fuses allow the entire device to be locked from external JTAG or other debug
access for code security. The security fuses can be written by a dedicated command, Set Secu-
rity Fuses (SSB). Once set, the only way to clear the security fuses is through the JTAG Chip
Erase command.
access for code security. The security fuses can be written by a dedicated command, Set Secu-
rity Fuses (SSB). Once set, the only way to clear the security fuses is through the JTAG Chip
Erase command.
Once the security fuses are set, the following Flash Controller commands will be unavailable
and return a lock error if attempted:
and return a lock error if attempted:
• Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2
• Erase All General-Purpose Fuses (EAGPF)
One error can be detected in the FSR register after issuing the command:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
14.9
Error Correcting Code
Error Correcting Code (ECC) logic is implemented to detect and correct errors that may arise in
the flash array. The ECC logic is able to detect two bit errors and correct one bit error per 32-bit
word in the array. An interrupt is requested upon detection of an ECC error if the ECC Error
Interrupt Enable (ECCE) bit in the Flash Control Register (FCR) is set is set. The ECCERR field
in Flash Status Register (FSR) indicates the ECC status of the words read from the flash.
the flash array. The ECC logic is able to detect two bit errors and correct one bit error per 32-bit
word in the array. An interrupt is requested upon detection of an ECC error if the ECC Error
Interrupt Enable (ECCE) bit in the Flash Control Register (FCR) is set is set. The ECCERR field
in Flash Status Register (FSR) indicates the ECC status of the words read from the flash.
Upon detection of an ECC error, the FERRADR register is updated with the failing address. If
the ECCE bit is set, FERRADR is loaded only on the first occurrence of an ECC error. Other-
wise, it is loaded on all occurrences. ECC checking is performed on a 64-bit basis, so an ECC
failure may be present in any of the two words that are output from the flash, not necessarily the
word that is addressed on the bus.
the ECCE bit is set, FERRADR is loaded only on the first occurrence of an ECC error. Other-
wise, it is loaded on all occurrences. ECC checking is performed on a 64-bit basis, so an ECC
failure may be present in any of the two words that are output from the flash, not necessarily the
word that is addressed on the bus.