Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
304
42023E–SAM–07/2013
ATSAM4L8/L4/L2
15. HSB Bus Matrix (HMATRIXB)
Rev: 1.3.0.3
15.1
Features
•
User Interface on peripheral bus
•
Configurable number of masters (up to 16)
•
Configurable number of slaves (up to 16)
•
One decoder for each master
•
Programmable arbitration for each slave
– Round-Robin
– Fixed priority
•
Programmable default master for each slave
– No default master
– Last accessed default master
– Fixed default master
•
One cycle latency for the first access of a burst
•
Zero cycle latency for default master
•
One special function register for each slave (not dedicated)
15.2
Overview
The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to
up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
15.3
Product Dependencies
In order to configure this module by accessing the user registers, other parts of the system must
be configured correctly, as described below.
be configured correctly, as described below.
15.3.1
Clocks
The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager.
This clock is disabled at reset, and can be enaabled in the Power Manager.
This clock is disabled at reset, and can be enaabled in the Power Manager.
15.4
Functional Description
15.4.1
Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master, and fixed default master.
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master, and fixed default master.