Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023E–SAM–07/2013

A CRC error can occur during the IN stage if the USBC detects a corrupted packet. The IN
packet will remain stored in the bank and RXINI will be set.

The user can check the Pn_CTR_STA_BK0/1.CRCERR bit in the pipe descriptor to see which
current bank has been affected.

There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors not related to CPU exceptions.

The processing host global interrupts are:

• The Device Connection Interrupt (DCONNI)

• The Device Disconnection Interrupt (DDISCI)

• The USB Reset Sent Interrupt (RSTI)

• The Downstream Resume Sent Interrupt (RSMEDI)

• The Upstream Resume Received Interrupt (RXRSMI)

• The Host Start of Frame Interrupt (HSOFI)

• The Host Wakeup Interrupt (HWUPI)

• The Pipe n Interrupt (PnINT)

There is no exception host global interrupt.

The processing host pipe interrupts are:

• The Received IN Data Interrupt (RXINI)

• The Transmitted OUT Data Interrupt (TXOUTI)

• The Transmitted SETUP Interrupt (TXSTPI)

• The Number of Busy Banks (NBUSYBK) interrupt 

The exception host pipe interrupts are:

• The Errorflow Interrupt (ERRORFI)

• The Pipe Error Interrupt (PERRI)

• The NAKed Interrupt (NAKEDI)

• The Received STALLed Interrupt (RXSTALLDI)

• The CRC Error Interrupt (CRCERRI)