Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
484
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 20-2. Basic Mode WDT Timing Diagram, Normal Operation
Figure 20-3. Basic Mode WDT Timing Diagram, No Clear within T
psel
20.5.1.6
Watchdog Reset
A watchdog reset will result in a reset and the code will start executing from the boot vector, refer
to
to
for details. If the Disable After Reset (DAR)
bit in the CTRL Register is zero, the WDT counter will restart counting from zero when the
watchdog reset is released.
watchdog reset is released.
If the CTRL.DAR bit is one the WDT will be disabled after a watchdog reset. Only the CTRL.EN
bit will be changed after the watchdog reset. However, if WDTAUTO fuse is configured to enable
the WDT after a watchdog reset, and the CTRL.FCD bit is zero, writing a one to the CTRL.DAR
bit will have no effect.
bit will be changed after the watchdog reset. However, if WDTAUTO fuse is configured to enable
the WDT after a watchdog reset, and the CTRL.FCD bit is zero, writing a one to the CTRL.DAR
bit will have no effect.
20.5.2
Window Mode
The window mode can protect against tight loops of runaway code. This is obtained by adding a
ban period to timeout period. During the ban period clearing the WDT counter is not allowed.
ban period to timeout period. During the ban period clearing the WDT counter is not allowed.
T
psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
t=t
0
T
psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
t=t
0