Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023E–SAM–07/2013

Figure 27-13. Combining a Read and Write Transfer

To generate this transfer:

1.

Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.

2.

Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.

3.

Wait until SR.RXRDY==1, then read first data byte received from RHR.

4.

Wait until SR.RXRDY==1, then read second data byte received from RHR.

5.

Wait until SR.TXRDY==1, then write first data byte to transfer to THR.

6.

Wait until SR.TXRDY==1, then write second data byte to transfer to THR.

Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers
with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of
CMDR.SADR must be written appropriately.

In 

 and 

, the grey boxes represent signals driven by the master, the

white boxes are driven by the slave.

To perform a master transmitter transfer: 

1.

Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the 
desired address and NBYTES value.

Figure 27-14. A Write Transfer with 10-bit Addressing

When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-
trolled. CMDR.REPSAME must be written to one when the address phase of the transfer should
consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard
specifies that such addressing is required when addressing a slave for reads using 10-bit
addressing.

To perform a master receiver transfer: 

TWD

SR.IDLE

TXRDY

S

SADR

R

A

DATA0

A

DATA1

Sr

DADR

W

A

DATA2

A

DATA3

NA

P

DATA2

THR

RXRDY

RHR

DATA3

DATA0

A

1

2

DATA3

Read 

TWI_RHR

S

SLAVE ADDRESS

1st 7 bits

P

A

DATA

RW A1

A2

SLAVE ADDRESS

2nd byte

AA

DATA

1

1

1

1

0

X

X

0