Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
782
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 29-3. IISC Clocks Generation
29.6.6
Mono
When the Transmit Mono (TXMONO) in the Mode Register is set, data written to the left channel
is duplicated to the right output channel.
is duplicated to the right output channel.
When the Receive Mono (RXMONO) in the Mode Register is set, data received from the left
channel is duplicated to the right channel.
channel is duplicated to the right channel.
29.6.7
Holding Registers
The IISC user interface includes a Receive Holding Register (RHR) and a Transmit Holding
Register (THR). RHR and THR are used to access audio samples for both audio channels.
Register (THR). RHR and THR are used to access audio samples for both audio channels.
When a new data word is available in the RHR register, the Receive Ready bit (RXRDY) in the
Status Register (SR) is set. Reading the RHR register will clear this bit.
Status Register (SR) is set. Reading the RHR register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous
data word has been read from the RHR register. Then, the Receive Overrun bit in the Status
Register will be set and bit i of the RXORCH field in the Status Register is set, where i is the cur-
rent receive channel number.
data word has been read from the RHR register. Then, the Receive Overrun bit in the Status
Register will be set and bit i of the RXORCH field in the Status Register is set, where i is the cur-
rent receive channel number.
When the THR register is empty, the Transmit Ready bit (TXRDY) in the Status Register (SR) is
set. Writing into the THR register will clear this bit.
set. Writing into the THR register will clear this bit.
A transmit underrun condition occurs if a new data word needs to be transmitted before it has
been written to the THR register. Then, the Transmit Underrun bit in the Status Register will be
set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit
channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is trans-
mitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current
transmit channel number is transmitted.
been written to the THR register. Then, the Transmit Underrun bit in the Status Register will be
set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit
channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is trans-
mitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current
transmit channel number is transmitted.
MR.MODE = SLAVE
Clock
divider
MR.DATALENGTH
GCLK_IISC
Clock
enable
Clock
divider
CR.CKEN/CKDIS
MR.IMCKMODE
MR.DATALENGTH
MR.IMCKFS
MR.IMCKMODE
1
0
IMCK pin output
Clock
enable
CR.CKEN/CKDIS
Internal
bit clock
bit clock
ISCK pin input
1
0
ISCK pin output
Internal
word clock
word clock
IWS pin input
1
0
IWS pin output