Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023E–SAM–07/2013

The specific configuration for each PEVC instance is listed in the following tables.

The module bus clocks listed here are connected to the system bus clocks. Refer to 

 for details.

The module Register Reset Values are listed below.

The following table defines generators and input events connected to the Peripheral Event Sys-
tem. It also specifies whether Event Shaper and Input Glitch Filter are implemented for this
generator, and if SleepWalking is available.

Module Clock Name

PEVC

CLK_PEVC

Register Reset Values

VERSION

0x00000200

PARAMETER

0x131F1204

BUSY

0x0002401F

Generators

0

PAD_EVT 0 - change on input pin

Yes

Yes

Yes

1

PAD_EVT 1 - change on input pin

Yes

Yes

Yes

2

PAD_EVT 2 - change on input pin

Yes

Yes

Yes

3

PAD_EVT 3 - change on input pin

Yes

Yes

Yes

4

GCLK 8 - rising edge

Yes

5

GCLK 9 - rising edge

Yes

6

AST - alarm event 0

Yes

Yes

7

Reserved

8

AST - periodic event 0

Yes

Yes

9

Reserved

10

AST - overflow event

Yes

Yes

11

ACIFC - AC0 VINP>VINN

12

ACIFC - AC1 VINP>VINN

13

ACIFC - AC2 VINP>VINN

14

ACIFC - AC3 VINP>VINN

15

ACIFC - AC0 VINP<VINN

16

ACIFC - AC1 VINP<VINN

17

ACIFC - AC2 VINP<VINN

18

ACIFC - AC3 VINP<VINN