Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023E–SAM–07/2013

In order to use this module, other parts of the system must be configured correctly, as described
below.

The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed
with I/O Controller lines. 

Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the
Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.

The clock for the ABDACB bus interface (CLK_ABDACB) is generated by the Power Manager. It
is recommended to disable the ABDACB before disabling the clock, to avoid freezing the
ABDACB in an undefined state. Before using the Audio Bitstream DAC, the user must ensure
that the Audio Bitstream DAC clock is enabled in the Power Manager.

The Audio Bitstream DAC requires a separate clock for the D/A conversion. This clock is pro-
vided by a generic clock which has to be set up in the System Control Interface (SCIF). The
frequency for this clock has to be set as described in 

. It is important that

this clock is accurate and has low jitter. Incorrect frequency will result in too fast or too slow play-
back (frequency shift), and too high jitter will add noise to the D/A conversion. For best
performance one should trade frequency accuracy (within some limits) for low jitter to obtain the
best performance as jitter will have large impact on the quality of the converted signal. 

The ABDACB is connected to the Peripheral DMA controller. Using DMA to transfer data sam-
ples requires the Peripheral DMA controller to be programmed before enabling the ABDACB. 

The ABDACB interrupt request line is connected to the NVIC. Using the ABDACB interrupt
requires the NVIC to be programmed first.

I/O Lines Description

DAC[0]

Output for channel 0

Output

DACN[0]

Inverted output for channel 0

Output

DAC[1]

Output for channel 1

Output

DACN[1]

Inverted output for channel 1

Output

CLK

Clock output for DAC

Output