Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
961
42023E–SAM–07/2013
ATSAM4L8/L4/L2
36.4
I/O Lines Description
Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped
sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and
OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to
IN[4n+3] and OUTn.
sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and
OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to
IN[4n+3] and OUTn.
36.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
below.
36.5.1
I/O Lines
The pins used for interfacing the GLOC may be multiplexed with I/O Controller lines. The pro-
grammer must first program the I/O Controller to assign the desired GLOC pins to their
peripheral function. If I/O lines of the GLOC are not used by the application, they can be used for
other purposes by the I/O Controller.
grammer must first program the I/O Controller to assign the desired GLOC pins to their
peripheral function. If I/O lines of the GLOC are not used by the application, they can be used for
other purposes by the I/O Controller.
It is only required to enable the GLOC inputs and outputs in use. Pullups for pins configured to
be used by the GLOC will be disabled.
be used by the GLOC will be disabled.
36.5.2
Clocks
The clock for the GLOC bus interface (CLK_GLOC) is generated by the Power Manager. This
clock is disabled at reset, and can be enabled in the Power Manager. It is recommended to dis-
able the GLOC before disabling the clock, to avoid freezing the module in an undefined state.
clock is disabled at reset, and can be enabled in the Power Manager. It is recommended to dis-
able the GLOC before disabling the clock, to avoid freezing the module in an undefined state.
Additionally, the GLOC depends on a dedicated Generic Clock (GCLK). The GCLK can be set to
a wide range of frequencies and clock sources, and must be enabled by the System Control
Interface (SCIF) before the GLOC filter can be used.
a wide range of frequencies and clock sources, and must be enabled by the System Control
Interface (SCIF) before the GLOC filter can be used.
36.5.3
Debug Operation
When an external debugger forces the CPU into debug mode, the GLOC continues normal
operation.
operation.
36.6
Functional Description
36.6.1
Enabling the Lookup Table Inputs
Since the inputs to each lookup table (LUT) unit can be multiplexed with other peripherals, each
input must be explicitly enabled by writing a one to the corresponding enable bit (AEN) in the
corresponding Control Register (CR).
input must be explicitly enabled by writing a one to the corresponding enable bit (AEN) in the
corresponding Control Register (CR).
If no inputs are enabled, the output OUTn will be the least significant bit in the TRUTHn register.
Table 36-1.
I/O Lines Description
Pin Name
Pin Description
Type
IN0-INm
Inputs to lookup tables
Input
OUT0-OUTn
Output from lookup tables
Output