Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
112
42023E–SAM–07/2013
ATSAM4L8/L4/L2
10.6.3
Speeding-up Sleep Modes Wake Up Times
The normal way for the Power Manager to enter WAIT mode involves automatically switching
the main clock to RCSYS before stopping all oscillators. During wake-up, the main clock is auto-
matically switched back from RCSYS to the oscillator selected before the WFI instruction was
executed. The delay needed to switch to/from the RCSYS oscillator is around three RCSYS
clock cycles, plus oscillator startup times when waking up.
the main clock to RCSYS before stopping all oscillators. During wake-up, the main clock is auto-
matically switched back from RCSYS to the oscillator selected before the WFI instruction was
executed. The delay needed to switch to/from the RCSYS oscillator is around three RCSYS
clock cycles, plus oscillator startup times when waking up.
It is possible to speed-up the enter/wake-up times for the WAIT modes by disabling the auto-
matic switch to RCSYS. This is only useful if a high frequency oscillator with a very fast startup
time is used. The user has to select the main clock source by writing a one to the corresponding
bit in the FASTSLEEP register. The device will not wake up correctly if the right oscillator in the
FASTSLEEP register is not selected.
matic switch to RCSYS. This is only useful if a high frequency oscillator with a very fast startup
time is used. The user has to select the main clock source by writing a one to the corresponding
bit in the FASTSLEEP register. The device will not wake up correctly if the right oscillator in the
FASTSLEEP register is not selected.
To have a fast wakeup time in WAIT and RETENTION power save mode, refer to
10.6.4
Divided APB Clocks
The clock generator in the Power Manager provides divided APBx clocks for use by peripherals
that require a prescaled APBx clock. This is described in the documentation for the relevant
modules.
that require a prescaled APBx clock. This is described in the documentation for the relevant
modules.
The divided clocks are directly maskable, and are stopped in Power Save modes where the
APBx clocks are stopped.
APBx clocks are stopped.
10.6.5
Reset Controller
The Reset Controller collects the various reset sources and generates resets for the device.
The device contains a Power-On Detector, which keeps the system reset until power is stable.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
It is also possible to reset the device by pulling the RESET_N pin low. This pin has an internal
pull-up, and does not need to be driven externally during normal operation.
pull-up, and does not need to be driven externally during normal operation.
lists these and other reset sources supported by the Reset Controller.
Table 10-2.
Reset Description
Reset source
Description
POR18 Reset
Supply voltage below the 1.8V power-on reset detector
threshold voltage
threshold voltage
External Reset
RESET_N pin asserted
BOD18 Reset
Supply voltage on VDDCORE below the 1.8V brownout
reset detector threshold voltage
reset detector threshold voltage
BOD33 Reset
Supply voltage on I/O below the 3.3V brownout reset
detector threshold voltage
detector threshold voltage
POR33 Reset
Supply voltage on I/O below the 3.3 V power-on reset
detector threshold voltage
detector threshold voltage
Watchdog Timer
See Watchdog Timer documentation
Backup Reset
Reset from backup mode when a wake up source occurs
OCD Reset
See On-Chip Debug and Test chapter