Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

42023E–SAM–07/2013

2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.

Notations:

C

b

 = total capacitance of one bus line in pF

t

clkpb

 = period of TWI peripheral bus clock

t

prescaled

 = period of TWI internal prescaled clock (see chapters on TWIM and TWIS)

The maximum t

HD;DAT

 has only to be met if the device does not stretch the LOW period (t

LOW-TWI

)

of TWCK.

Figure 42-17. JTAG Interface Signals

JTAG2

JTAG3

JTAG1

JTAG4

JTAG0

TMS/TDI

TCK

TDO

JTAG5

JTAG6

JTAG7

JTAG8

JTAG9

JTAG10

Boundary

Scan Inputs

Boundary

Scan Outputs