Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

42023E–SAM–07/2013

Figure 13-2. PLL with Control Logic and Filters

Before the PLL is enabled it must be set up correctly. The 

PLL Oscillator Select field (

PLLOSC)

selects a source for the reference clock. The PLL Multiply Factor (PLLMUL) and PLL Division
Factor (PLLDIV) fields must be written with the multiplication and division factors, respectively.
The PLLMUL must always be greater than 1, creating the PLL frequency:

f

vco

 = (PLLMUL+1)/PLLDIV • f

REF

, if PLLDIV >0

f

vco

 = 2•(PLLMUL+1) • f

REF

, if PLLDIV = 0

The PLL Options (PLLOPT) field should be configured to proper values according to the PLL
operating frequency. The PLLOPT field can also be configured to divide the output frequency of
the PLL by 2 and Wide-Bandwidth mode, which allows faster startup time and out-of-lock time.

It is not possible to change any of the PLL configuration bits when the PLL is enabled, Any write
to PLLn while the PLL is enabled will be discarded.

After setting up the PLL, the PLL is enabled by writing a one to the PLL Enable (PLLEN) bit in
the PLLn register. 

The PLL is disabled by writing a zero to the PLL Enable (PLLEN) bit in the PLLn register. After
disabling the PLL, the PLL configuration fields becomes writable.

The lock signal for each PLL is available as a PLLLOCKn flag in the PCLKSR register. If the lock
for some reason is lost, the PLLLOCKLOSTn flag in PCLKSR register will be set. An interrupt
can be generated on a 0 to 1 transition of these bits.

Phase 

Detector

Output 

Divider

Source 

clocks

PLLOSC

PLLOPT[0]

PLLMUL

Lock bit

Mask

PLL clock

Input 

Divider

PLLDIV

1/2

PLLOPT[1]

0

1

VCO

f

vco

f

PLL

Lock

Counter

f

REF