Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

42023E–SAM–07/2013

To prevent unexpected writes due to software bugs, write access to the RC80MCR register is
protected by a locking mechanism. For details refer to 

. The RC80M is automatically switched off in certain sleep modes to reduce power consump-

tion, as described in 

.

Rev: 1.0.2.0

The generic clocks can be sourced by two special prescalers to increase the generic clock fre-
quency precision.

These prescalers are named the High Resolution Prescaler (HRP) and the Fractional Prescaler
(FP).

The HRP is a 24-bit counter that can generate a very accurate clock waveform. The clock
obtained has 50% duty cycle. 

Figure 13-8. High Resolution Prescaler Generation

The HRP is enabled by writing a one to the High Resolution Prescaler Enable (HRPEN) bit in the
High Resolution Prescaler Control Register (HRPCR). 

The user can select a clock source for the HRP by writing to the Clock Selection (CKSEL) field of
the HRPCR register. 

The user must configure the High Resolution Prescaler Clock (HRPCLK) frequency by writing to
the High Resolution Count (HRCOUNT) field of the High Resolution Counter (HRPCR) register.
This results in the output frequency:

f

HRPCLK

 = f

SRC

 /

 (2*(HRCOUNT+1))

The CKSEL field can not be changed dynamically but the HRCOUNT field can be changed on-
the-fly. 

The FP generates a clock whose average frequency is more precise than the HRP. However,
this clock frequency is subject to jitter around the target clock frequency. This jitter influence can
be decreased by dividing this clock with the GCLK divider. Moreover the duty cycle of this clock
is not precisely 50%.

Divider

CKSEL

HRPCLK

HRCOUNT

Mask

HRPEN