Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
248
42023E–SAM–07/2013
ATSAM4L8/L4/L2
13.7.25
Generic Clock Control
Name: GCCTRL
Access Type:
Read/Write
Reset Value:
0x00000000
There is one GCCTRL register per generic clock in the design.
• DIV: Division Factor
The number of DIV bits for each generic clock is as shown in the “Generic Clock number of DIV bits” table in the SCIF Module
Configuration section.
• OSCSEL: Oscillator Select
Selects the source clock for the generic clock. Refer to the “Generic Clock Sources” table in the SCIF Module Configuration
section.
• DIVEN: Divide Enable
0: The generic clock equals the undivided source clock.
1: The generic clock equals the source clock divided by 2*(DIV+1).
• CEN: Clock Enable
0: The generic clock is disabled.
1: The generic clock is enabled.
31
30
29
28
27
26
25
24
DIV[15:8]
23
22
21
20
19
18
17
16
DIV[7:0]
15
14
13
12
11
10
9
8
-
-
-
OSCSEL[4:0]
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DIVEN
CEN