Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
316
42023E–SAM–07/2013
ATSAM4L8/L4/L2
15.6
Module Configuration
The specific configuration for each HMATRIX instance is listed in the following tables.The mod-
ule bus clocks listed here are connected to the system bus clocks. Refer to
ule bus clocks listed here are connected to the system bus clocks. Refer to
for details.
15.6.1
Bus Matrix Connections
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU IDCODE master interface.
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU IDCODE master interface.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG5 is
associated with the Internal SRAM Slave Interface.
in the table below can be used to index the HMATRIX control registers. For example, SCFG5 is
associated with the Internal SRAM Slave Interface.
Accesses to unused areas returns an error result to the master requesting such an access.
Table 15-3.
HMATRIX Clocks
Clock Name
Description
CLK_HMATRIX
Clock for the HMATRIX bus interface
Table 15-4.
High Speed Bus Masters
Master 0
CPU IDCODE
Master 1
CPU SYS
Master 2
SMAP
Master 3
PDCA
Master 4
USBC
Master 5
CRCCU
Table 15-5.
High Speed Bus Slaves
Slave 0
Internal Flash
Slave 1
AHB-APB Bridge A
Slave 2
AHB-APB Bridge B
Slave 3
AHB-APB Bridge C
Slave 4
AHB-APB Bridge D
Slave 5
Internal SRAM
Slave 6
Internal SRAM for cache
Slave 7
AESA