Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

42023E–SAM–07/2013

IN packets are sent by the USBC device controller upon IN requests from the host.

The endpoint and its descriptor in RAM must be pre configured (see section 

 for more details).

When the current bank is clear, the TXINI and FIFO Control (UECONn.FIFOCON) bits will be set
simultaneously. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable
(TXINE) bit in UECONn is one.

TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt. This has no effect on the endpoint FIFO.

The user writes the IN data to the bank referenced by the EPn descriptor and allows the USBC
to send the data by writing a one to the FIFO Control Clear (UECONnCLR.FIFOCONC) bit. This
will also cause a switch to the next bank if the IN endpoint is composed of multiple banks. The
TXINI and FIFOCON bits will be updated accordingly.

TXINI should always be cleared before clearing FIFOCON to avoid missing an TXINI event.

Figure 17-9. Example of an IN endpoint with one data bank

Figure 17-10. Example of an IN endpoint with two data banks

IN

DATA

(bank 0)

ACK

TXINI

FIFOCON

HW

write data to CPU

BANK 0

SW

SW

SW

SW

IN

NAK

write data to CPU

BANK 0

IN

DATA

(bank 0)

ACK

TXINI

FIFOCON

write data to CPU

BANK 0

SW

SW

SW

SW

IN

DATA

(bank 1)

ACK

write data to CPU

BANK 1

SW

HW

write data to CPU

BANK0