Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
580
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 24-4. Transmitter Status
24.6.2.3
Asynchronous Receiver
If the USART is configured in an asynchronous operating mode (MR.SYNC is zero), the receiver
will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by
the Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight con-
secutive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample
will determine the logical value on the line, resulting in bit values being determined at the middle
of the bit period.
will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by
the Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight con-
secutive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample
will determine the logical value on the line, resulting in bit values being determined at the middle
of the bit period.
The number of data bits, endianess, parity mode, and stop bits are selected by the same bits
and fields as for the transmitter (MR.CHRL, MR.MODE9, MR.MSBF, MR.PAR, and
MR.NBSTOP). The synchronization mechanism will only consider one stop bit, regardless of the
used protocol, and when the first stop bit has been sampled, the receiver will automatically begin
looking for a new start bit, enabling resynchronization even if there is a protocol mismatch.
and fields as for the transmitter (MR.CHRL, MR.MODE9, MR.MSBF, MR.PAR, and
MR.NBSTOP). The synchronization mechanism will only consider one stop bit, regardless of the
used protocol, and when the first stop bit has been sampled, the receiver will automatically begin
looking for a new start bit, enabling resynchronization even if there is a protocol mismatch.
and
mode.
Figure 24-5. Asynchronous Start Bit Detection
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Start
Bit
Write
THR
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
TXRDY
TXEMPTY
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
0
1
2
3
4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
D0
Sampling