Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

42023E–SAM–07/2013

is not received within the time defined in THeader_Maximum, the Lin Header Time-out error
(CSR.LINHTE) is generated (see 

). An interrupt request is generated if

IMR.LINHTE is set. Writing a one to CR.RSTSTA will clear CSR.LINHTE, CSR.LINBK, and
CSR.LINID.

Figure 24-29. Header Reception

See also 

. 

Synchronization is only done by the slave, and can be disabled by writing a one to the Synchro-
nization Disable bit in the LIN Mode Register (LINMR.SYNCDIS). If the Sync byte is not 0x55, an
Inconsistent Sync Field error is generated, and the LIN Inconsistend Sync Field Error bit in CSR
(CSR.LINISFE) is set. An interrupt request is generated if the LINISFE bit in IMR is set.
CSR.LINISFE is cleared by writing a one to CR.RSTSTA. The time between falling edges is
measured by a 19-bit counter, driven by the sampling clock (see 

Figure 24-30. Sync Field

The counter starts when the Sync field start bit is detected, and continues for eight bit periods. If
the deviation is within ±15% (see below), the 16 most significant bits (counter value divided by 8)
becomes the new clock divider (LINBRR.LINCD), and the three least significant bits (the remain-
der) becomes the new fractional part (LINBRR.LINFP).

Break Field

13 dominant bits (at 0)

Break

Delimiter

1 recessive bit

(at 1)

Start

Bit

1

0

1

0

1

0

1

0

Stop

Bit

Start

Bit

ID0 ID1 ID2

ID4

ID3

ID6

ID5

ID7

Stop

Bit

Synch Byte = 0x55

Baud Rate

Clock

RXD

Write US_CR

With RSTSTA=1

US_LINIR

LINID

Start

bit

Stop

bit

Synch Field

8 Tbit

2 Tbit

2 Tbit

2 Tbit

2 Tbit