Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
748
42023E–SAM–07/2013
ATSAM4L8/L4/L2
• Write to the relevant register fields in the TWIS with appropriate values and leave those in
TWIM as zeros, or vice versa; or
• Write to the relevant register fields in both the TWIM and the TWIS with the same values.
28.8.3.1
Bus Timing
The Timing Register (TR) is used to control the timing of bus signals driven by the TWIS. TR
describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling
can be selected through TR.EXP.
describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling
can be selected through TR.EXP.
TR has the following fields:
TLOWS: Prescaled clock cycles used to time SMBUS timeout T
LOW:SEXT
.
TTOUT: Prescaled clock cycles used to time SMBUS timeout T
TIMEOUT
.
SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time T
SU_DAT
.
EXP: Specifies the clock prescaler setting used for the SMBUS timeouts.
When the TWIS is in HS-mode, the data hold count is set by writing to the HDDAT field in the
HS-mode Timing Register (HSTR).
HS-mode Timing Register (HSTR).
Figure 28-6. Bus Timing Diagram
f
PRESCALED
f
CLK_TWIS
2
EXP
1
+
(
)
-------------------------
=
S
t
HD:STA
t
LOW
t
SU:DAT
t
HIGH
t
HD:DAT
t
LOW
P
t
SU:STO
Sr
t
SU:STA
t
SU:DAT