Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
1000
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
After waking up from STANDBY power save mode, perform a software reset of the TCC if you are
using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
8 - When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or
WAVEB registers will not cause a hardware exception. Errata reference: 11468
WAVEB registers will not cause a hardware exception. Errata reference: 11468
Fix/Workaround:
None
9 - If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an
immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata
reference: 12155
immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata
reference: 12155
Fix/Workaround:
None
39.4 Revision E
39.4.1 Device
1 - If APB clock is stopped and GCLK clock is running, APB read access to read-
synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as
a consequence debug operation is impossible. Errata reference: 10416
synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as
a consequence debug operation is impossible. Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is
running. To recover from this situation, power cycle the device or reset the device using the
RESETN pin.
running. To recover from this situation, power cycle the device or reset the device using the
RESETN pin.
2 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software
reset can reset the GCLK generators using XOSC32K as source clock. Errata reference:
12164
reset can reset the GCLK generators using XOSC32K as source clock. Errata reference:
12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K failure.
39.4.2 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a write access to a
DFLL register can freeze the device. Errata reference: 9905
DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL
module.
module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values
during the locking sequence, an out of bounds interrupt will be generated. These interrupts
will be generated even if the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669
during the locking sequence, an out of bounds interrupt will be generated. These interrupts
will be generated even if the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround: