Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
103
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
14.8.5 Generic Clock Generator Division
This register allows the user to configure one of the generic clock generators, as specified in the GENDIV.ID bit group.
To write to the GENDIV register, do a 32-bit write with all configurations and the ID.
To write to the GENDIV register, do a 32-bit write with all configurations and the ID.
To read the GENDIV register, first do an 8-bit write to the GENDIV.ID bit group with the ID of the generic clock generator
whose configuration is to be read, and then read the GENDIV register.
whose configuration is to be read, and then read the GENDIV register.
Name:
GENDIV
Offset:
0x8
Reset:
0x00000000
Property:
-
z
Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 23:8 – DIV[15:0]: Division Factor
These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has
can be seen in
These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has
can be seen in
. Writes to bits above the specified number will be ignored.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIV[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DIV[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0