Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
Page of 1018
130
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
15.8.10 APBC Mask
Name:
APBCMASK
Offset:
0x20
Reset:
0x00010000
Property:
Write-Protected
z
Bits 31:21 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bit 20 – I2S: I2S APB Clock Enable
0: The APBC clock for the I2S is stopped.
1: The APBC clock for the I2S is enabled.
z
Bit 19 – PTC: PTC APB Clock Enable
0: The APBC clock for the PTC is stopped.
1: The APBC clock for the PTC is enabled.
z
Bit 18 – DAC: DAC APB Clock Enable
0: The APBC clock for the DAC is stopped.
1: The APBC clock for the DAC is enabled.
z
Bit 17 – AC: AC APB Clock Enable
0: The APBC clock for the AC is stopped.
1: The APBC clock for the AC is enabled.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
I2S
PTC
DAC
AC
ADC
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
1
Bit
15
14
13
12
11
10
9
8
TC7
TC6
TC5
TC4
TC3
TCC2
TCC1
TCC0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
PAC2
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0