Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
136
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
15.8.14 Reset Cause
Name:
RCAUSE
Offset:
0x38
Reset:
0x01
Property:
-
z
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 6 – SYST: System Reset Request
This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more
details.
This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more
details.
z
Bit 5 – WDT: Watchdog Reset
This flag is set if a Watchdog Timer reset occurs.
This flag is set if a Watchdog Timer reset occurs.
z
Bit 4 – EXT: External Reset
This flag is set if an external reset occurs.
This flag is set if an external reset occurs.
z
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 2 – BOD33: Brown Out 33 Detector Reset
This flag is set if a BOD33 reset occurs.
This flag is set if a BOD33 reset occurs.
z
Bit 1 – BOD12: Brown Out 12 Detector Reset
This flag is set if a BOD12 reset occurs.
This flag is set if a BOD12 reset occurs.
z
Bit 0 – POR: Power On Reset
This flag is set if a POR occurs.
This flag is set if a POR occurs.
Bit
7
6
5
4
3
2
1
0
SYST
WDT
EXT
BOD33
BOD12
POR
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
1