Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

z

PLL Lock Lost (LOCKL): Indicates that a falling edge has been detected on the Lock bit during normal operation mode.

z

PLL Lock Timer Timeout (LTTO): This interrupt flag indicates that the software defined time DPLLCTRLB.LTIME has 
elapsed since the start of the FDPLL96M.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear 
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one 
to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the 
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled, or the SYSCTRL is reset. See Interrupt Flag Status and Clear (

details on how to clear interrupt flags.

All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request 
to the NVIC. Refer to 

 for details. The user must read the INTFLAG 

register to determine which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 

Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to other clock 
domains. The status of this synchronization can be read from the Power and Clocks Status register (PCLKSR). Before 
writing to any of the DFLL48M control registers, the user must check that the DFLL Ready bit (PCLKSR.DFLLRDY) in 
PCLKSR is set to one. When this bit is set, the DFLL48M can be configured and CLK_DFLL48M is ready to be used. Any 
write to any of the DFLL48M control registers while DFLLRDY is zero will be ignored. An interrupt is generated on a zero-
to-one transition of DFLLRDY if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set.

In order to read from any of the DFLL48M configuration registers, the user must request a read synchronization by 
writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If 
DFLLSYNC.READREQ is not written before a read, a synchronization will be started, and the bus will be halted until the 
synchronization is complete. Reading the DFLL48M registers when the DFLL48M is disabled will not halt the bus.

The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from the peripheral 
bus. As a consequence, the prescaler registers require synchronization when written or read. The synchronization 
results in a delay from when the initialization of the write or read operation begins until the operation is complete.

The write-synchronization is triggered by a write to the BOD33 control register. The Synchronization Ready bit 
(PCLKSR.B33SRDY) in the PCLKSR register will be cleared when the write-synchronization starts and set when the 
write-synchronization is complete. When the write-synchronization is ongoing (PCLKSR.B33SRDYis zero), an attempt to 
do any of the following will cause the peripheral bus to stall until the synchronization is complete: 

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Writing to the BOD33control register

z

Reading the BOD33 control register that was written

The user can either poll PCLKSR.B33SRDY or use the INTENSET.B33SRDY interrupts to check when the 
synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation 
will be completed after the ongoing read/write operation is synchronized.