Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
177
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.8.7 32kHz Internal Oscillator (OSC32K) Control
Name:
OSC32K
Offset:
0x18
Reset:
0x003F0080
Property:
Write-Protected
z
Bits 31:23 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 22:16 – CALIB[6:0]: Oscillator Calibration
These bits control the oscillator calibration.
This value must be written by the user.
Factory calibration values can be loaded from the non-volatile memory. Refer to
These bits control the oscillator calibration.
This value must be written by the user.
Factory calibration values can be loaded from the non-volatile memory. Refer to
z
Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 12 – WRTLOCK: Write Lock
This bit locks the OSC32K register for futur writes to fix the OSC32K configuration.
0: The OSC32K configuration is not locked.
1: The OSC32K configuration is locked.
This bit locks the OSC32K register for futur writes to fix the OSC32K configuration.
0: The OSC32K configuration is not locked.
1: The OSC32K configuration is locked.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CALIB[6:0]
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
WRTLOCK
STARTUP[2:0]
Access
R
R
R
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
EN1K
EN32K
ENABLE
Access
R/W
R/W
R
R
R/W
R/W
R/W
R
Reset
1
0
0
0
0
0
0
0