Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
197
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.8.19 DPLL Control B
Name:
DPLLCTRLB
Offset:
0x4C
Reset:
0x00000000
Property:
Write-Protected
z
Bits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 26:16 – DIV[10:0]: Clock Divider
These bits are used to set the XOSC clock source division factor. Refer to
These bits are used to set the XOSC clock source division factor. Refer to
.
z
Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 12 – LBYPASS: Lock Bypass
0: Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1: Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
0: Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1: Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
z
Bit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit
31
30
29
28
27
26
25
24
DIV[10:8]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIV[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
LBYPASS
LTIME[2:0]
Access
R
R
R
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
REFCLK[1:0]
WUF
LPEN
FILTER[1:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0